The demand for non-volatile semiconductor memory devices, which are small in size and large scale in capacity, has increased rapidly in recent years. Compared with NOR type flash memories, NAND type flash memories, which can expect higher integration and larger memory capacity, have attracted attention.
Widths and intervals (Line and Space) of wirings in non-volatile semiconductor memory devices, such as a NAND type flash memory, become small as ultra-fine processing technologies of photolithography advance (scaling is carried out). Generally, the size of NAND strings becomes smaller in accordance with the advance in its feature size (chip process generations). As a result, large capacity NAND type flash memories are realizable. When the sizes of NAND strings become small, it will be necessary to make the size of transfer transistors smaller. However, when the size of transfer transistors become small, the Line and Space of a gate wiring GC and a first wiring layer M0 which connect the word line WL connected to the NAND string and transfer transistors, cannot be fully secured. As a result, the withstanding voltage between word lines WL will also decrease. It becomes difficult to avoid defects, such as short-circuiting of word lines by dielectric breakdown, and it becomes difficult to maintain the reliability of NAND type flash memories. While Japanese Patent Publications (Kokai) 2004-79857, 2004-55617 describe the above NAND type flash memory dealing with such problems, these publications are hereby incorporated as references.